# ETH: MAC FIFO underflow, transmission stalled on queue 3

- **ID:** `embedded/eth-mac-fifo-underflow`
- **Domain:** embedded
- **Category:** network_error
- **Verification:** ai_generated
- **Fix Rate:** 76%

## Root Cause

Ethernet MAC transmit FIFO empties before the packet is fully sent due to insufficient DMA bandwidth or low-priority queue scheduling.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32Cube_FW_H7_V1.11.0 | active | — | — |
| LWIP 2.1.3 | active | — | — |
| FreeRTOSv202212.01 | active | — | — |
| IAR EWARM 9.50.1 | active | — | — |

## Workarounds

1. **Increase DMA burst length for ETH TX: set ETH_DMABMR->FB = 0x1 (fixed burst) and ETH_DMABMR->PBL = 0x20 (32-beat burst) in HAL_ETH_Init().** (82% success)
   ```
   Increase DMA burst length for ETH TX: set ETH_DMABMR->FB = 0x1 (fixed burst) and ETH_DMABMR->PBL = 0x20 (32-beat burst) in HAL_ETH_Init().
   ```
2. **Prioritize ETH DMA channel over other DMA channels using NVIC priority and DMA stream priority (low/high) in CubeMX.** (78% success)
   ```
   Prioritize ETH DMA channel over other DMA channels using NVIC priority and DMA stream priority (low/high) in CubeMX.
   ```
3. **Enable ETH TX FIFO threshold programming: set ETH_MACFCR->TFE = 1 and configure ETH_MACFCR->TFT to 0x10 (16 bytes threshold) to trigger DMA earlier.** (80% success)
   ```
   Enable ETH TX FIFO threshold programming: set ETH_MACFCR->TFE = 1 and configure ETH_MACFCR->TFT to 0x10 (16 bytes threshold) to trigger DMA earlier.
   ```

## Dead Ends

- **Increasing Ethernet buffer size in lwIPopts.h (e.g., PBUF_POOL_SIZE from 16 to 32)** — Larger buffers increase latency but do not solve MAC FIFO underflow caused by DMA starvation. (85% fail)
- **Disabling interrupt coalescing in ETH DMA** — More interrupts can increase CPU load and worsen DMA bandwidth contention. (75% fail)
- **Reducing TCP window size to 1** — Severely limits throughput and does not address the underlying FIFO drain issue. (90% fail)