# NVIC: priority grouping mismatch between ISR and main code

- **ID:** `embedded/nvic-priority-group-mismatch`
- **Domain:** embedded
- **Category:** config_error
- **Verification:** ai_generated
- **Fix Rate:** 82%

## Root Cause

NVIC priority grouping (e.g., group vs. subpriority bits) is configured differently in interrupt handlers and the main initialization path, causing undefined behavior when nesting interrupts.

## Workarounds

1. **Ensure NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4) is called exactly once at the start of main(), before any peripheral initialization. Example: void main(void) { NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* 4 bits for pre-emption, 0 for subpriority */ HAL_Init(); SystemClock_Config(); ... }** (90% success)
   ```
   Ensure NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4) is called exactly once at the start of main(), before any peripheral initialization. Example: void main(void) { NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* 4 bits for pre-emption, 0 for subpriority */ HAL_Init(); SystemClock_Config(); ... }
   ```
2. **Use a static assert to check that all modules use the same grouping. For example, in FreeRTOS, ensure configPRIO_BITS matches the hardware grouping.** (85% success)
   ```
   Use a static assert to check that all modules use the same grouping. For example, in FreeRTOS, ensure configPRIO_BITS matches the hardware grouping.
   ```

## Dead Ends

- **** — Disabling all interrupts globally does not fix the grouping mismatch; interrupts still fire with inconsistent priority logic. (60% fail)
- **** — Changing the grouping value inside an ISR leads to immediate hard fault or priority inversion because the NVIC state is inconsistent. (80% fail)