embedded config_error ai_generated true

NVIC：中断优先级分组在主代码与中断服务程序中不一致

NVIC: priority grouping mismatch between ISR and main code

ID: embedded/nvic-priority-group-mismatch

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82%修复率
85%置信度
1证据数
2024-03-15首次发现

根因分析

NVIC优先级分组（如组优先级与子优先级位数分配）在中断处理函数与主初始化路径中配置不一致，导致中断嵌套时行为未定义。

English

NVIC priority grouping (e.g., group vs. subpriority bits) is configured differently in interrupt handlers and the main initialization path, causing undefined behavior when nesting interrupts.

generic

官方文档

https://developer.arm.com/documentation/dui0552/a/cortex-m3-peripherals/nested-vectored-interrupt-controller/priority-grouping

解决方案

  1. Ensure NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4) is called exactly once at the start of main(), before any peripheral initialization. Example: void main(void) { NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* 4 bits for pre-emption, 0 for subpriority */ HAL_Init(); SystemClock_Config(); ... }
  2. Use a static assert to check that all modules use the same grouping. For example, in FreeRTOS, ensure configPRIO_BITS matches the hardware grouping.

无效尝试

常见但无效的做法:

  1. 60% 失败

    Disabling all interrupts globally does not fix the grouping mismatch; interrupts still fire with inconsistent priority logic.

  2. 80% 失败

    Changing the grouping value inside an ISR leads to immediate hard fault or priority inversion because the NVIC state is inconsistent.