# SPI: CRC error on receive, calculated 0x1A2B expected 0x3C4D

- **ID:** `embedded/spi-crc-error-receive-mode`
- **Domain:** embedded
- **Category:** protocol_error
- **Verification:** ai_generated
- **Fix Rate:** 88%

## Root Cause

SPI CRC mismatch due to noise on lines, incorrect polynomial configuration, or data length mismatch between master and slave.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32Cube_FW_G4 V1.5.0 | active | — | — |
| SPI HAL V1.4.0 | active | — | — |

## Workarounds

1. **Verify SPI CRC polynomial matches between master and slave: `SPI_CR1_CRCPOLY` register must be identical. Use `SPI_CR1_CRCEN` to enable CRC.** (90% success)
   ```
   Verify SPI CRC polynomial matches between master and slave: `SPI_CR1_CRCPOLY` register must be identical. Use `SPI_CR1_CRCEN` to enable CRC.
   ```
2. **Add software CRC check after each transaction as fallback: compute CRC16-CCITT on received data and compare.** (85% success)
   ```
   Add software CRC check after each transaction as fallback: compute CRC16-CCITT on received data and compare.
   ```
3. **Reduce SPI clock to below 5 MHz to improve signal integrity on noisy lines.** (80% success)
   ```
   Reduce SPI clock to below 5 MHz to improve signal integrity on noisy lines.
   ```

## Dead Ends

- **** — Increasing SPI clock speed exacerbates signal integrity issues, making CRC errors more frequent. (80% fail)
- **** — Reseating cables does not fix incorrect polynomial settings in software. (50% fail)