{
  "id": "embedded/spi-crc-mismatch-on-slave",
  "signature": "SPI: CRC mismatch on slave, received 0xA5 expected 0x5A",
  "signature_zh": "SPI：从设备CRC不匹配，接收到0xA5，期望0x5A",
  "regex": "SPI: CRC mismatch on slave, received 0x[0-9A-F]+ expected 0x[0-9A-F]+",
  "domain": "embedded",
  "category": "protocol_error",
  "subcategory": null,
  "root_cause": "CRC calculation mismatch between master and slave due to different polynomial settings or data order (LSB-first vs MSB-first).",
  "root_cause_type": "generic",
  "root_cause_zh": "主设备和从设备之间CRC计算不匹配，原因是多项式设置不同或数据顺序（LSB优先与MSB优先）不一致。",
  "versions": [
    {
      "version": "STM32F4 SPI driver v1.4.0",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    },
    {
      "version": "HAL SPI v1.3.2",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    }
  ],
  "os_specific": {},
  "dead_ends": [
    {
      "action": "",
      "why_fails": "Disabling CRC removes error detection, potentially allowing corrupted data to be accepted silently.",
      "fail_rate": 0.6,
      "condition": "",
      "sources": []
    },
    {
      "action": "",
      "why_fails": "Swapping roles does not fix the underlying CRC configuration mismatch; the error will persist on the new master.",
      "fail_rate": 0.9,
      "condition": "",
      "sources": []
    }
  ],
  "workarounds": [
    {
      "action": "Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit",
      "success_rate": 0.9,
      "how": "Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit",
      "condition": "",
      "sources": []
    },
    {
      "action": "Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`",
      "success_rate": 0.8,
      "how": "Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`",
      "condition": "",
      "sources": []
    }
  ],
  "workarounds_zh": [
    "Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit",
    "Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`"
  ],
  "transition_graph": {
    "leads_to": [],
    "preceded_by": [],
    "frequently_confused_with": []
  },
  "official_doc_url": "https://www.st.com/resource/en/application_note/an4013-spi-protocol-and-crc-on-stm32-mcus-stmicroelectronics.pdf",
  "official_doc_section": null,
  "error_code": "SPI_ERR_CRC_MISMATCH",
  "verification_tier": "ai_generated",
  "confidence": 0.86,
  "fix_success_rate": 0.85,
  "resolvable": "true",
  "first_seen": "2023-09-28",
  "last_confirmed": "2024-06-01",
  "last_updated": "2024-06-01",
  "evidence_count": 1,
  "tags": [],
  "locale": "en",
  "aliases": []
}