# SPI: CRC mismatch on slave, received 0xA5 expected 0x5A

- **ID:** `embedded/spi-crc-mismatch-on-slave`
- **Domain:** embedded
- **Category:** protocol_error
- **Error Code:** `SPI_ERR_CRC_MISMATCH`
- **Verification:** ai_generated
- **Fix Rate:** 85%

## Root Cause

CRC calculation mismatch between master and slave due to different polynomial settings or data order (LSB-first vs MSB-first).

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32F4 SPI driver v1.4.0 | active | — | — |
| HAL SPI v1.3.2 | active | — | — |

## Workarounds

1. **Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit** (90% success)
   ```
   Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit
   ```
2. **Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`** (80% success)
   ```
   Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`
   ```

## Dead Ends

- **** — Disabling CRC removes error detection, potentially allowing corrupted data to be accepted silently. (60% fail)
- **** — Swapping roles does not fix the underlying CRC configuration mismatch; the error will persist on the new master. (90% fail)