# SPI: DMA CRC error, received CRC mismatch on slave, expected 0x1A2B got 0x3C4D

- **ID:** `embedded/spi-dma-crc-error-stm32`
- **Domain:** embedded
- **Category:** protocol_error
- **Verification:** ai_generated
- **Fix Rate:** 92%

## Root Cause

CRC calculation mismatch between master and slave due to different polynomial settings or DMA transfer length misalignment in STM32 SPI hardware CRC mode.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32Cube_FW_H7 v1.10.0 | active | — | — |
| ARM GCC v12.2.1 | active | — | — |
| SPI HAL driver v2.4.0 | active | — | — |

## Workarounds

1. **Set identical CRC polynomial on both master and slave: SPI_InitTypeDef.CRCPolynomial = 7; and ensure SPI_CRCPR register matches. For DMA, set SPI_CR2.TXDMAEN/RXDMAEN after configuring CRC length.** (95% success)
   ```
   Set identical CRC polynomial on both master and slave: SPI_InitTypeDef.CRCPolynomial = 7; and ensure SPI_CRCPR register matches. For DMA, set SPI_CR2.TXDMAEN/RXDMAEN after configuring CRC length.
   ```
2. **Align DMA transfer size to CRC length: if CRC is 16-bit, ensure total transfer length is multiple of 2 bytes. Use HAL_SPI_TransmitReceive_DMA() with buffer sizes that include CRC bytes.** (90% success)
   ```
   Align DMA transfer size to CRC length: if CRC is 16-bit, ensure total transfer length is multiple of 2 bytes. Use HAL_SPI_TransmitReceive_DMA() with buffer sizes that include CRC bytes.
   ```

## Dead Ends

- **Disable SPI CRC hardware and implement software CRC** — Software CRC adds latency and may conflict with DMA timing; hardware CRC mismatch root cause remains unaddressed. (80% fail)
- **Swap master and slave roles** — Role swap does not fix polynomial or length mismatch; error may move but persists. (90% fail)