# SPI: DMA FIFO overrun, data lost on channel 2

- **ID:** `embedded/spi-dma-fifo-overrun`
- **Domain:** embedded
- **Category:** runtime_error
- **Verification:** ai_generated
- **Fix Rate:** 78%

## Root Cause

SPI DMA transfer rate exceeds FIFO drain speed, causing data loss in the RX FIFO.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32Cube_FW_H7_V1.11.0 | active | — | — |
| FreeRTOSv202212.01 | active | — | — |
| ARM GCC 12.2.1 | active | — | — |

## Workarounds

1. **Reduce SPI baud rate prescaler (e.g., from 2 to 4) in MX_SPI1_Init(): hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; then regenerate code.** (85% success)
   ```
   Reduce SPI baud rate prescaler (e.g., from 2 to 4) in MX_SPI1_Init(): hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; then regenerate code.
   ```
2. **Enable SPI RX FIFO threshold interrupt and use DMA with circular mode: set hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; and configure DMA in circular mode.** (90% success)
   ```
   Enable SPI RX FIFO threshold interrupt and use DMA with circular mode: set hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; and configure DMA in circular mode.
   ```
3. **Use DMA flow controller with burst transfers: configure DMA2_Stream0 with DMA_SxCR_PBURST and DMA_SxCR_MBURST enabled.** (75% success)
   ```
   Use DMA flow controller with burst transfers: configure DMA2_Stream0 with DMA_SxCR_PBURST and DMA_SxCR_MBURST enabled.
   ```

## Dead Ends

- **Increasing SPI clock speed to match DMA rate** — Higher clock speed worsens the FIFO overflow issue as data arrives faster. (90% fail)
- **Disabling DMA and using polling mode** — Polling mode reduces throughput and may cause CPU starvation in real-time systems. (70% fail)
- **Adding software delay loops in the DMA ISR** — Delays in ISR increase latency and can cause other interrupts to be missed. (80% fail)