# SPI DMA: misaligned buffer address 0x2000FF01, data transfer aborted

- **ID:** `embedded/spi-dma-misaligned-buffer`
- **Domain:** embedded
- **Category:** config_error
- **Verification:** ai_generated
- **Fix Rate:** 90%

## Root Cause

DMA buffer address is not aligned to the DMA controller's required boundary (typically 4 or 16 bytes), causing a transfer error or bus fault.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32H743 | active | — | — |
| ARM Cortex-M7 r1p1 | active | — | — |
| HAL_DMA v2.2.0 | active | — | — |

## Workarounds

1. **Allocate DMA buffers using aligned memory macros. For GCC, use __attribute__((aligned(16))). For CMSIS, use DMA_BUFFER_ALIGNED.** (95% success)
   ```
   Allocate DMA buffers using aligned memory macros. For GCC, use __attribute__((aligned(16))). For CMSIS, use DMA_BUFFER_ALIGNED.
   ```
2. **Use dynamic memory allocation from a dedicated aligned heap, e.g., pvPortMallocAligned from FreeRTOS or memalign.** (90% success)
   ```
   Use dynamic memory allocation from a dedicated aligned heap, e.g., pvPortMallocAligned from FreeRTOS or memalign.
   ```

## Dead Ends

- **Use memcpy to copy data to a temporary buffer before DMA transfer** — Adds latency and memory overhead; if the temporary buffer is also not aligned due to compiler padding, the error persists. (50% fail)
- **Disable DMA and use polling SPI instead** — Reduces throughput significantly and may cause CPU starvation in high-speed applications. (80% fail)
- **Change DMA FIFO threshold to bypass alignment check** — FIFO threshold does not affect address alignment requirements; misalignment still causes AHB bus error. (95% fail)