SPI_DMA_INCOMPLETE embedded data_error ai_generated partial

SPI: DMA transfer incomplete, expected 256 bytes but only 128 bytes received on channel 1

ID: embedded/spi-dma-transfer-incomplete

Also available as: JSON · Markdown · 中文
80%Fix Rate
87%Confidence
1Evidence
2023-09-05First Seen

Version Compatibility

VersionStatusIntroducedDeprecatedNotes
STM32Cube_FW_F7 v1.17.0 active — — —
STM32Cube_FW_G4 v1.6.0 active — — —
DMA HAL Driver v2.3.0 active — — —

Root Cause

The SPI DMA transfer was prematurely terminated due to a timeout, FIFO overflow, or slave device deasserting chip select mid-transfer.

generic

中文

SPI DMA传输因超时、FIFO溢出或从设备在传输中途取消片选而过早终止。

Official Documentation

https://www.st.com/resource/en/application_note/an4031-dma-controller-application-examples-stmicroelectronics.pdf

Workarounds

  1. 85% success Add a DMA transfer complete callback (HAL_SPI_TxRxCpltCallback) to verify the received byte count and re-initiate the transfer if incomplete. 
    Add a DMA transfer complete callback (HAL_SPI_TxRxCpltCallback) to verify the received byte count and re-initiate the transfer if incomplete.
  2. 70% success Enable SPI CRC checking to detect data corruption and retry the transfer on CRC mismatch. 
    Enable SPI CRC checking to detect data corruption and retry the transfer on CRC mismatch.

中文步骤

  1. Add a DMA transfer complete callback (HAL_SPI_TxRxCpltCallback) to verify the received byte count and re-initiate the transfer if incomplete.
  2. Enable SPI CRC checking to detect data corruption and retry the transfer on CRC mismatch.

Dead Ends

Common approaches that don't work:

  1. Increase the SPI clock speed to transfer data faster 80% fail

    Higher clock speed can exacerbate timing issues and cause more FIFO overflows, worsening the problem.

  2. Disable DMA and use polling SPI transfer instead 75% fail

    Polling transfers can block the CPU for long periods, causing real-time task failures and still not resolving the root cause of incomplete transfers.