{
  "id": "embedded/spi-dma-transfer-size-mismatch",
  "signature": "SPI: DMA transfer size mismatch, expected 256 bytes but transferred 128 bytes on channel 1",
  "signature_zh": "SPI：DMA 传输大小不匹配，通道 1 上预期 256 字节但实际传输 128 字节",
  "regex": "SPI: DMA transfer size mismatch, expected \\d+ bytes but transferred \\d+ bytes on channel \\d+",
  "domain": "embedded",
  "category": "runtime_error",
  "subcategory": null,
  "root_cause": "DMA configuration uses incorrect data size or burst settings, or SPI FIFO threshold misaligned with DMA transfer length.",
  "root_cause_type": "generic",
  "root_cause_zh": "DMA 配置使用了错误的数据大小或突发设置，或 SPI FIFO 阈值与 DMA 传输长度不对齐。",
  "versions": [
    {
      "version": "STM32CubeMX 6.10.0",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    },
    {
      "version": "HAL SPI Driver 2.3.1",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    },
    {
      "version": "ARM GCC 13.2.1",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    }
  ],
  "os_specific": {},
  "dead_ends": [
    {
      "action": "Increase SPI baud rate to speed up transfer",
      "why_fails": "Baud rate does not affect DMA transfer size; mismatch is due to configuration, not speed.",
      "fail_rate": 0.95,
      "condition": "",
      "sources": []
    },
    {
      "action": "Set DMA to circular mode to repeat transfer",
      "why_fails": "Circular mode repeats the same incorrect size; it does not fix the underlying mismatch and may cause buffer overflow.",
      "fail_rate": 0.85,
      "condition": "",
      "sources": []
    }
  ],
  "workarounds": [
    {
      "action": "Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;",
      "success_rate": 0.95,
      "how": "Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;",
      "condition": "",
      "sources": []
    },
    {
      "action": "Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).",
      "success_rate": 0.88,
      "how": "Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).",
      "condition": "",
      "sources": []
    }
  ],
  "workarounds_zh": [
    "Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;",
    "Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0)."
  ],
  "transition_graph": {
    "leads_to": [],
    "preceded_by": [],
    "frequently_confused_with": []
  },
  "official_doc_url": "https://www.st.com/resource/en/application_note/an4031-dma-controller-on-stm32-mcus-stmicroelectronics.pdf",
  "official_doc_section": null,
  "error_code": null,
  "verification_tier": "ai_generated",
  "confidence": 0.87,
  "fix_success_rate": 0.92,
  "resolvable": "true",
  "first_seen": "2025-05-03",
  "last_confirmed": "2024-06-01",
  "last_updated": "2024-06-01",
  "evidence_count": 1,
  "tags": [],
  "locale": "en",
  "aliases": []
}