# SPI: DMA transfer size mismatch, expected 256 bytes but transferred 128 bytes on channel 1

- **ID:** `embedded/spi-dma-transfer-size-mismatch`
- **Domain:** embedded
- **Category:** runtime_error
- **Verification:** ai_generated
- **Fix Rate:** 92%

## Root Cause

DMA configuration uses incorrect data size or burst settings, or SPI FIFO threshold misaligned with DMA transfer length.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32CubeMX 6.10.0 | active | — | — |
| HAL SPI Driver 2.3.1 | active | — | — |
| ARM GCC 13.2.1 | active | — | — |

## Workarounds

1. **Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;** (95% success)
   ```
   Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;
   ```
2. **Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).** (88% success)
   ```
   Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).
   ```

## Dead Ends

- **Increase SPI baud rate to speed up transfer** — Baud rate does not affect DMA transfer size; mismatch is due to configuration, not speed. (95% fail)
- **Set DMA to circular mode to repeat transfer** — Circular mode repeats the same incorrect size; it does not fix the underlying mismatch and may cause buffer overflow. (85% fail)