{
  "id": "embedded/spi-ssi-fifo-underrun",
  "signature": "SPI: SSI FIFO underrun on channel 0, data transmission aborted",
  "signature_zh": "SPI：SSI FIFO下溢在通道0上，数据传输中止",
  "regex": "SPI: SSI FIFO underrun on channel \\d+, data transmission aborted",
  "domain": "embedded",
  "category": "runtime_error",
  "subcategory": null,
  "root_cause": "SPI controller's transmit FIFO emptied before new data was written by DMA or CPU, causing underrun and aborting the frame due to lack of data.",
  "root_cause_type": "generic",
  "root_cause_zh": "SPI控制器的发送FIFO在DMA或CPU写入新数据之前已清空，导致下溢并因缺少数据而中止帧传输。",
  "versions": [
    {
      "version": "Synopsys DW_apb_ssi v4.01a",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    },
    {
      "version": "STM32H743 HAL 1.11.0",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    },
    {
      "version": "Linux kernel 5.15.0",
      "introduced": null,
      "deprecated": null,
      "removed": null,
      "behavior_change": null,
      "status": "active"
    }
  ],
  "os_specific": {},
  "dead_ends": [
    {
      "action": "",
      "why_fails": "Increasing SPI clock speed worsens underrun because it accelerates FIFO drain, making time-to-fill smaller.",
      "fail_rate": 0.95,
      "condition": "",
      "sources": []
    },
    {
      "action": "",
      "why_fails": "Doubling FIFO depth via hardware configuration does not help if CPU/DMA latency remains high; underrun occurs at same rate.",
      "fail_rate": 0.8,
      "condition": "",
      "sources": []
    }
  ],
  "workarounds": [
    {
      "action": "Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);",
      "success_rate": 0.88,
      "how": "Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);",
      "condition": "",
      "sources": []
    },
    {
      "action": "Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.",
      "success_rate": 0.9,
      "how": "Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.",
      "condition": "",
      "sources": []
    }
  ],
  "workarounds_zh": [
    "Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);",
    "Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4."
  ],
  "transition_graph": {
    "leads_to": [],
    "preceded_by": [],
    "frequently_confused_with": []
  },
  "official_doc_url": "https://www.synopsys.com/dw/ipdir.php?ds=spi_ssi",
  "official_doc_section": null,
  "error_code": "0x800F0001",
  "verification_tier": "ai_generated",
  "confidence": 0.82,
  "fix_success_rate": 0.87,
  "resolvable": "true",
  "first_seen": "2023-11-05",
  "last_confirmed": "2024-06-01",
  "last_updated": "2024-06-01",
  "evidence_count": 1,
  "tags": [],
  "locale": "en",
  "aliases": []
}