# SPI: SSI FIFO underrun on channel 0, data transmission aborted

- **ID:** `embedded/spi-ssi-fifo-underrun`
- **Domain:** embedded
- **Category:** runtime_error
- **Error Code:** `0x800F0001`
- **Verification:** ai_generated
- **Fix Rate:** 87%

## Root Cause

SPI controller's transmit FIFO emptied before new data was written by DMA or CPU, causing underrun and aborting the frame due to lack of data.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| Synopsys DW_apb_ssi v4.01a | active | — | — |
| STM32H743 HAL 1.11.0 | active | — | — |
| Linux kernel 5.15.0 | active | — | — |

## Workarounds

1. **Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);** (88% success)
   ```
   Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);
   ```
2. **Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.** (90% success)
   ```
   Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.
   ```

## Dead Ends

- **** — Increasing SPI clock speed worsens underrun because it accelerates FIFO drain, making time-to-fill smaller. (95% fail)
- **** — Doubling FIFO depth via hardware configuration does not help if CPU/DMA latency remains high; underrun occurs at same rate. (80% fail)