# UART: overrun error on USART1, data lost

- **ID:** `embedded/uart-overrun-error`
- **Domain:** embedded
- **Category:** runtime_error
- **Error Code:** `USART_SR_ORE`
- **Verification:** ai_generated
- **Fix Rate:** 80%

## Root Cause

UART receive buffer overrun because the CPU failed to read data before the next byte arrived, typically due to high interrupt latency or insufficient DMA buffering.

## Version Compatibility

| Version | Status | Introduced | Deprecated |
|---------|--------|------------|------------|
| STM32Cube_FW_F4 v1.27.0 | active | — | — |
| FreeRTOS v10.4.6 | active | — | — |
| GCC ARM Embedded 12.2.1 | active | — | — |

## Workarounds

1. **Enable UART DMA for reception with a circular buffer: configure DMA with peripheral-to-memory transfer, set buffer size to 256 bytes, and use half-transfer/full-transfer interrupts to process data.** (85% success)
   ```
   Enable UART DMA for reception with a circular buffer: configure DMA with peripheral-to-memory transfer, set buffer size to 256 bytes, and use half-transfer/full-transfer interrupts to process data.
   ```
2. **Increase UART FIFO threshold (if hardware supports): set USART_CR3_DMAT to enable DMA, or configure RTO (receive timeout) to flush buffer periodically.** (75% success)
   ```
   Increase UART FIFO threshold (if hardware supports): set USART_CR3_DMAT to enable DMA, or configure RTO (receive timeout) to flush buffer periodically.
   ```
3. **Reduce interrupt priority of other peripherals to ensure UART ISR executes promptly: use NVIC_SetPriority(USART1_IRQn, 0) for highest priority.** (70% success)
   ```
   Reduce interrupt priority of other peripherals to ensure UART ISR executes promptly: use NVIC_SetPriority(USART1_IRQn, 0) for highest priority.
   ```

## Dead Ends

- **Increase UART baud rate to reduce data arrival rate** — Higher baud rate increases data rate, worsening the overrun condition. (95% fail)
- **Disable UART interrupts and poll manually** — Polling increases CPU load and may miss data entirely, leading to more overruns. (80% fail)
- **Add a delay in the UART ISR** — Delays in ISR increase interrupt latency, causing more overruns. (90% fail)