embedded network_error ai_generated true

以太网：MAC FIFO下溢，队列3传输停滞

ETH: MAC FIFO underflow, transmission stalled on queue 3

ID: embedded/eth-mac-fifo-underflow

其他格式: JSON · Markdown 中文 · English
76%修复率
83%置信度
1证据数
2024-06-10首次发现

版本兼容性

版本状态引入弃用备注
STM32Cube_FW_H7_V1.11.0 active — — —
LWIP 2.1.3 active — — —
FreeRTOSv202212.01 active — — —
IAR EWARM 9.50.1 active — — —

根因分析

以太网MAC发送FIFO在数据包完全发送前变空，原因是DMA带宽不足或低优先级队列调度。

English

Ethernet MAC transmit FIFO empties before the packet is fully sent due to insufficient DMA bandwidth or low-priority queue scheduling.

generic

官方文档

https://www.st.com/resource/en/application_note/dm00352730-ethernet-mac-dma-controller-on-stm32-mcus-stmicroelectronics.pdf

解决方案

  1. Increase DMA burst length for ETH TX: set ETH_DMABMR->FB = 0x1 (fixed burst) and ETH_DMABMR->PBL = 0x20 (32-beat burst) in HAL_ETH_Init().
  2. Prioritize ETH DMA channel over other DMA channels using NVIC priority and DMA stream priority (low/high) in CubeMX.
  3. Enable ETH TX FIFO threshold programming: set ETH_MACFCR->TFE = 1 and configure ETH_MACFCR->TFT to 0x10 (16 bytes threshold) to trigger DMA earlier.

无效尝试

常见但无效的做法:

  1. Increasing Ethernet buffer size in lwIPopts.h (e.g., PBUF_POOL_SIZE from 16 to 32) 85% 失败

    Larger buffers increase latency but do not solve MAC FIFO underflow caused by DMA starvation.

  2. Disabling interrupt coalescing in ETH DMA 75% 失败

    More interrupts can increase CPU load and worsen DMA bandwidth contention.

  3. Reducing TCP window size to 1 90% 失败

    Severely limits throughput and does not address the underlying FIFO drain issue.