embedded hardware_error ai_generated true

SPI: chip select glitch detected on GPIO line, causing false slave selection

ID: embedded/spi-cs-glitch-on-gpio

Also available as: JSON · Markdown · 中文
90%Fix Rate
86%Confidence
1Evidence
2024-06-01First Seen

Root Cause

The chip select (CS) GPIO line is driven by software or has insufficient drive strength, causing a brief low pulse (glitch) during GPIO toggling, which falsely selects or deselects the SPI slave.

generic

中文

片选GPIO线由软件驱动或驱动强度不足，在GPIO切换时产生短暂低电平脉冲（毛刺），导致SPI从设备被误选中或取消选中。

Official Documentation

https://www.st.com/resource/en/application_note/an4031-stm32-spi-protocol.pdf

Workarounds

  1. 95% success Enable the SPI peripheral's hardware NSS (automatic chip select) if available. Example on STM32: hspi.Init.NSS = SPI_NSS_HARD_OUTPUT; then configure the CS pin as SPI_NSS alternate function. 
    Enable the SPI peripheral's hardware NSS (automatic chip select) if available. Example on STM32: hspi.Init.NSS = SPI_NSS_HARD_OUTPUT; then configure the CS pin as SPI_NSS alternate function.
  2. 85% success Add a 10kΩ pull-up resistor on the CS line to hold it high during GPIO transitions, and set the GPIO output to open-drain with a weak drive. 
    Add a 10kΩ pull-up resistor on the CS line to hold it high during GPIO transitions, and set the GPIO output to open-drain with a weak drive.

中文步骤

  1. Enable the SPI peripheral's hardware NSS (automatic chip select) if available. Example on STM32: hspi.Init.NSS = SPI_NSS_HARD_OUTPUT; then configure the CS pin as SPI_NSS alternate function.
  2. Add a 10kΩ pull-up resistor on the CS line to hold it high during GPIO transitions, and set the GPIO output to open-drain with a weak drive.

Dead Ends

Common approaches that don't work:

  1. 70% fail

    Adding a delay before toggling CS does not eliminate the glitch; the glitch occurs during the transition itself.

  2. 60% fail

    Changing the GPIO output speed to high increases the glitch amplitude due to faster slew rate, making the problem worse.