SPI_ERR_CRC_MISMATCH embedded protocol_error ai_generated true

SPI：从设备CRC不匹配，接收到0xA5，期望0x5A

SPI: CRC mismatch on slave, received 0xA5 expected 0x5A

ID: embedded/spi-crc-mismatch-on-slave

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85%修复率
86%置信度
1证据数
2023-09-28首次发现

版本兼容性

版本状态引入弃用备注
STM32F4 SPI driver v1.4.0 active — — —
HAL SPI v1.3.2 active — — —

根因分析

主设备和从设备之间CRC计算不匹配，原因是多项式设置不同或数据顺序（LSB优先与MSB优先）不一致。

English

CRC calculation mismatch between master and slave due to different polynomial settings or data order (LSB-first vs MSB-first).

generic

官方文档

https://www.st.com/resource/en/application_note/an4013-spi-protocol-and-crc-on-stm32-mcus-stmicroelectronics.pdf

解决方案

  1. Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit
  2. Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`

无效尝试

常见但无效的做法:

  1. 60% 失败

    Disabling CRC removes error detection, potentially allowing corrupted data to be accepted silently.

  2. 90% 失败

    Swapping roles does not fix the underlying CRC configuration mismatch; the error will persist on the new master.