SPI_ERR_CRC_MISMATCH embedded protocol_error ai_generated true

SPI: CRC mismatch on slave, received 0xA5 expected 0x5A

ID: embedded/spi-crc-mismatch-on-slave

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85%Fix Rate
86%Confidence
1Evidence
2023-09-28First Seen

Version Compatibility

VersionStatusIntroducedDeprecatedNotes
STM32F4 SPI driver v1.4.0 active — — —
HAL SPI v1.3.2 active — — —

Root Cause

CRC calculation mismatch between master and slave due to different polynomial settings or data order (LSB-first vs MSB-first).

generic

中文

主设备和从设备之间CRC计算不匹配，原因是多项式设置不同或数据顺序（LSB优先与MSB优先）不一致。

Official Documentation

https://www.st.com/resource/en/application_note/an4013-spi-protocol-and-crc-on-stm32-mcus-stmicroelectronics.pdf

Workarounds

  1. 90% success Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit 
    Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit
  2. 80% success Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }` 
    Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`

中文步骤

  1. Align CRC polynomial and bit order on both devices: set `SPI_CR1_CRCPOLY` to the same value (e.g., 0x07) and ensure both use MSB-first by clearing the LSBFIRST bit
  2. Implement a software CRC check after SPI transfer as a fallback: `if (crc8(data, len) != expected_crc) { retry_transfer(); }`

Dead Ends

Common approaches that don't work:

  1. 60% fail

    Disabling CRC removes error detection, potentially allowing corrupted data to be accepted silently.

  2. 90% fail

    Swapping roles does not fix the underlying CRC configuration mismatch; the error will persist on the new master.