embedded runtime_error ai_generated true

SPI: DMA FIFO overrun, data lost on channel 2

ID: embedded/spi-dma-fifo-overrun

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78%Fix Rate
85%Confidence
1Evidence
2024-03-15First Seen

Version Compatibility

VersionStatusIntroducedDeprecatedNotes
STM32Cube_FW_H7_V1.11.0 active — — —
FreeRTOSv202212.01 active — — —
ARM GCC 12.2.1 active — — —

Root Cause

SPI DMA transfer rate exceeds FIFO drain speed, causing data loss in the RX FIFO.

generic

中文

SPI DMA传输速率超过FIFO排空速度，导致接收FIFO中数据丢失。

Official Documentation

https://www.st.com/resource/en/application_note/dm00204416-spi-dma-communication-on-stm32-microcontrollers-stmicroelectronics.pdf

Workarounds

  1. 85% success Reduce SPI baud rate prescaler (e.g., from 2 to 4) in MX_SPI1_Init(): hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; then regenerate code. 
    Reduce SPI baud rate prescaler (e.g., from 2 to 4) in MX_SPI1_Init(): hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; then regenerate code.
  2. 90% success Enable SPI RX FIFO threshold interrupt and use DMA with circular mode: set hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; and configure DMA in circular mode. 
    Enable SPI RX FIFO threshold interrupt and use DMA with circular mode: set hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; and configure DMA in circular mode.
  3. 75% success Use DMA flow controller with burst transfers: configure DMA2_Stream0 with DMA_SxCR_PBURST and DMA_SxCR_MBURST enabled. 
    Use DMA flow controller with burst transfers: configure DMA2_Stream0 with DMA_SxCR_PBURST and DMA_SxCR_MBURST enabled.

中文步骤

  1. Reduce SPI baud rate prescaler (e.g., from 2 to 4) in MX_SPI1_Init(): hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; then regenerate code.
  2. Enable SPI RX FIFO threshold interrupt and use DMA with circular mode: set hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; and configure DMA in circular mode.
  3. Use DMA flow controller with burst transfers: configure DMA2_Stream0 with DMA_SxCR_PBURST and DMA_SxCR_MBURST enabled.

Dead Ends

Common approaches that don't work:

  1. Increasing SPI clock speed to match DMA rate 90% fail

    Higher clock speed worsens the FIFO overflow issue as data arrives faster.

  2. Disabling DMA and using polling mode 70% fail

    Polling mode reduces throughput and may cause CPU starvation in real-time systems.

  3. Adding software delay loops in the DMA ISR 80% fail

    Delays in ISR increase latency and can cause other interrupts to be missed.