embedded runtime_error ai_generated true

SPI: DMA transfer size mismatch, expected 256 bytes but transferred 128 bytes on channel 1

ID: embedded/spi-dma-transfer-size-mismatch

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92%Fix Rate
87%Confidence
1Evidence
2025-05-03First Seen

Version Compatibility

VersionStatusIntroducedDeprecatedNotes
STM32CubeMX 6.10.0 active — — —
HAL SPI Driver 2.3.1 active — — —
ARM GCC 13.2.1 active — — —

Root Cause

DMA configuration uses incorrect data size or burst settings, or SPI FIFO threshold misaligned with DMA transfer length.

generic

中文

DMA 配置使用了错误的数据大小或突发设置，或 SPI FIFO 阈值与 DMA 传输长度不对齐。

Official Documentation

https://www.st.com/resource/en/application_note/an4031-dma-controller-on-stm32-mcus-stmicroelectronics.pdf

Workarounds

  1. 95% success Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256; 
    Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;
  2. 88% success Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0). 
    Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).

中文步骤

  1. Align DMA data size with SPI data size: ensure DMA_SxCR->PSIZE and MSIZE match SPI data width (e.g., 8-bit for SPI 8-bit frames). Set DMA_NNDT register to exact number of transfers: DMA1_Stream3->NDTR = 256;
  2. Disable SPI FIFO by setting SPI_CR2->FRXTH = 0 and use 8-bit data frames to match DMA byte transfers; adjust DMA burst settings to single transfers (MBURST = 0, PBURST = 0).

Dead Ends

Common approaches that don't work:

  1. Increase SPI baud rate to speed up transfer 95% fail

    Baud rate does not affect DMA transfer size; mismatch is due to configuration, not speed.

  2. Set DMA to circular mode to repeat transfer 85% fail

    Circular mode repeats the same incorrect size; it does not fix the underlying mismatch and may cause buffer overflow.