0x800F0001 embedded runtime_error ai_generated true

SPI：SSI FIFO下溢在通道0上，数据传输中止

SPI: SSI FIFO underrun on channel 0, data transmission aborted

ID: embedded/spi-ssi-fifo-underrun

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87%修复率
82%置信度
1证据数
2023-11-05首次发现

版本兼容性

版本状态引入弃用备注
Synopsys DW_apb_ssi v4.01a active — — —
STM32H743 HAL 1.11.0 active — — —
Linux kernel 5.15.0 active — — —

根因分析

SPI控制器的发送FIFO在DMA或CPU写入新数据之前已清空，导致下溢并因缺少数据而中止帧传输。

English

SPI controller's transmit FIFO emptied before new data was written by DMA or CPU, causing underrun and aborting the frame due to lack of data.

generic

官方文档

https://www.synopsys.com/dw/ipdir.php?ds=spi_ssi

解决方案

  1. Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);
  2. Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.

无效尝试

常见但无效的做法:

  1. 95% 失败

    Increasing SPI clock speed worsens underrun because it accelerates FIFO drain, making time-to-fill smaller.

  2. 80% 失败

    Doubling FIFO depth via hardware configuration does not help if CPU/DMA latency remains high; underrun occurs at same rate.