0x800F0001 embedded runtime_error ai_generated true

SPI: SSI FIFO underrun on channel 0, data transmission aborted

ID: embedded/spi-ssi-fifo-underrun

Also available as: JSON · Markdown · 中文
87%Fix Rate
82%Confidence
1Evidence
2023-11-05First Seen

Version Compatibility

VersionStatusIntroducedDeprecatedNotes
Synopsys DW_apb_ssi v4.01a active — — —
STM32H743 HAL 1.11.0 active — — —
Linux kernel 5.15.0 active — — —

Root Cause

SPI controller's transmit FIFO emptied before new data was written by DMA or CPU, causing underrun and aborting the frame due to lack of data.

generic

中文

SPI控制器的发送FIFO在DMA或CPU写入新数据之前已清空，导致下溢并因缺少数据而中止帧传输。

Official Documentation

https://www.synopsys.com/dw/ipdir.php?ds=spi_ssi

Workarounds

  1. 88% success Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size); 
    Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);
  2. 90% success Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4. 
    Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.

中文步骤

  1. Enable SPI FIFO underrun interrupt and in ISR, write dummy data to keep transmission alive: HAL_SPI_Abort(&hspi); then restart with HAL_SPI_Transmit_DMA(&hspi, pData, Size);
  2. Increase DMA burst size to 4 or 8 words to ensure FIFO stays filled; set DMA control register to burst size 4.

Dead Ends

Common approaches that don't work:

  1. 95% fail

    Increasing SPI clock speed worsens underrun because it accelerates FIFO drain, making time-to-fill smaller.

  2. 80% fail

    Doubling FIFO depth via hardware configuration does not help if CPU/DMA latency remains high; underrun occurs at same rate.